"FPGA-Based Annealing Processor with Time-Division Multiplexing."

Kasho Yamamoto et al. (2019)

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DOI: 10.1587/TRANSINF.2019PAP0002

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type: Journal Article

metadata version: 2025-01-19

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Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
FPGA-Based Annealing Processor with Time-Division Multiplexing. IEICE Trans. Inf. Syst. 102-D(12): 2295-2305 (2019)

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