"Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog ..."

Chengjie Zang, Shinji Kimura (2009)

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DOI: 10.1587/TRANSFUN.E92.A.1454

access: closed

type: Journal Article

metadata version: 2020-04-11

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Chengjie Zang, Shinji Kimura:
Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1454-1463 (2009)

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