"A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP ..."

Xiongxin Zhao et al. (2013)

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DOI: 10.1587/TRANSFUN.E96.A.2623

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type: Journal Article

metadata version: 2022-05-04

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Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto:
A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2623-2632 (2013)

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