"Noise-power-area optimised design procedure for OTAs with complementary ..."

Devarshi Mrinal Das et al. (2020)

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DOI: 10.1049/IET-CDS.2019.0259

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type: Journal Article

metadata version: 2022-04-09

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Devarshi Mrinal Das, Kashyap Barot, Abhishek Srivastava, Maryam Shojaei Baghini:
Noise-power-area optimised design procedure for OTAs with complementary input transistors for neural amplifiers. IET Circuits Devices Syst. 14(5): 702-706 (2020)

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