"Development of low-complexity all-digital frequency locked loop as 500 MHz ..."

Sigit Yuwono et al. (2014)

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DOI: 10.1049/IET-CDS.2013.0175

access: closed

type: Journal Article

metadata version: 2022-11-02

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Sigit Yuwono, Seok-Kyun Han, Giwan Yoon, Han-Jin Cho, Sang-Gug Lee:
Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array. IET Circuits Devices Syst. 8(2): 73-81 (2014)

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