"VLSI architectures for high speed and low power implementation of 5/3 ..."

Usha Bhanu Nageswaran, A. Chilambuchelvan (2016)

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DOI: 10.1504/IJCSE.2016.076213

access: closed

type: Journal Article

metadata version: 2023-09-30

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Usha Bhanu Nageswaran, A. Chilambuchelvan:
VLSI architectures for high speed and low power implementation of 5/3 lifting discrete wavelet transform. Int. J. Comput. Sci. Eng. 12(2/3): 254-263 (2016)

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