"Power-aware high level evaluation model of interconnect length of on-chip ..."

Xiaojun Wang et al. (2018)

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DOI: 10.1504/IJCSE.2018.096030

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type: Journal Article

metadata version: 2025-06-11

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Xiaojun Wang, Feng Shi, Yi-Zhuo Wang, Hong Zhang, Xu Chen, Wen-Fei Fu:
Power-aware high level evaluation model of interconnect length of on-chip memory network topology. Int. J. Comput. Sci. Eng. 17(4): 422-431 (2018)

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