"Delay caused by resistive opens in interconnecting lines."

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras (2009)

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DOI: 10.1016/J.VLSI.2008.11.001

access: closed

type: Journal Article

metadata version: 2020-02-20

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Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras:
Delay caused by resistive opens in interconnecting lines. Integr. 42(3): 286-293 (2009)

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