"Fast Multiplier Generator for FPGAs with LUT based Partial Product ..."

Ahmet Kakacak et al. (2017)

> Home

Details and statistics

DOI: 10.1016/J.VLSI.2016.12.012

access: closed

type: Journal Article

metadata version: 2021-11-16

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/integration/KakacakGCGU17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/integration/KakacakGCGU17
Ahmet Kakacak, Aydin Emre Guzel, Ozan Cihangir, Sezer Gören, H. Fatih Ugurdag:
Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression. Integr. 57: 147-157 (2017)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.