"Reconfigurable very high throughput low latency VLSI (FPGA) design ..."

Jubin Mitra, Tapan Kumar Nayak (2017)

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DOI: 10.1016/J.VLSI.2016.09.005

access: closed

type: Journal Article

metadata version: 2020-02-20

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Jubin Mitra, Tapan Kumar Nayak:
Reconfigurable very high throughput low latency VLSI (FPGA) design architecture of CRC 32. Integr. 56: 1-14 (2017)

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