"Low Power Low Latency Floorplan‐aware Path Synthesis in ..."

Priyajit Mukherjee, Santanu Chattopadhyay (2017)

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DOI: 10.1016/J.VLSI.2017.02.010

access: closed

type: Journal Article

metadata version: 2020-02-20

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Priyajit Mukherjee, Santanu Chattopadhyay:
Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design. Integr. 58: 167-188 (2017)

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