"An efficient architecture of truncated booth multiplier for AI application."

Shareefa Fairoose P., Ashutosh Mishra (2026)

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DOI: 10.1016/J.VLSI.2025.102544

access: closed

type: Journal Article

metadata version: 2025-11-15

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Shareefa Fairoose P., Ashutosh Mishra:
An efficient architecture of truncated booth multiplier for AI application. Integr. 106: 102544 (2026)

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