"ESegNet-ILT: An end-to-end mask optimization method in VLSI design flow ..."

Hui Xu et al. (2025)

> Home

Details and statistics

DOI: 10.1016/J.VLSI.2025.102512

access: closed

type: Journal Article

metadata version: 2025-09-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/integration/XuXZSLMLH25
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/integration/XuXZSLMLH25
Hui Xu, Yong Xue, Yu Zhang, Xia Sun, Jiale Li, Ruijun Ma, Huaguo Liang, Zhengfeng Huang:
ESegNet-ILT: An end-to-end mask optimization method in VLSI design flow based on enhanced SegNet. Integr. 105: 102512 (2025)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.