"Power-aware partitioning and test time reduction for 3D-SoC."

Sabyasachee Banerjee et al. (2024)

> Home

Details and statistics

DOI: 10.1007/S11334-022-00479-X

access: closed

type: Journal Article

metadata version: 2024-08-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/isse/BanerjeeMBD24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/isse/BanerjeeMBD24
Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya, Debesh K. Das:
Power-aware partitioning and test time reduction for 3D-SoC. Innov. Syst. Softw. Eng. 20(3): 485-498 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.