"Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC ..."

Debashis Mandal, T. K. Bhattacharyya (2008)

> Home

Details and statistics

DOI: 10.4304/JCP.3.4.31-38

access: open

type: Journal Article

metadata version: 2021-02-25

- view
  authority control:
- export record
  dblp key:
  - journals/jcp/MandalB08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcp/MandalB08
Debashis Mandal, T. K. Bhattacharyya:
Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design. J. Comput. 3(4): 31-38 (2008)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.