"A High Throughput and Pipelined Implementation of the LUKS on FPGA."

Xiaochao Li et al. (2020)

> Home

Details and statistics

DOI: 10.1142/S0218126620500759

access: closed

type: Journal Article

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jcsc/LiWZLCW20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcsc/LiWZLCW20
Xiaochao Li, Kongcheng Wu, Qi Zhang, Shaoyu Lin, Yihui Chen, Shen Yuong Wong:
A High Throughput and Pipelined Implementation of the LUKS on FPGA. J. Circuits Syst. Comput. 29(5): 2050075:1-2050075:20 (2020)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.