Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID"An 8-Bit 0.333-2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS."
Dengquan Li et al. (2015)
- Dengquan Li
, Liang Zhang, Zhangming Zhu, Yintang Yang:
An 8-Bit 0.333-2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS. J. Circuits Syst. Comput. 24(6): 1550093:1-1550093:14 (2015)
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2020-08-25 16:58 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
