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"Improved Redundant Binary Adder Realization in FPGA."

Satya Ranjan Sahu, Bandan Kumar Bhoi, Manoranjan Pradhan (2021)

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DOI: 10.1142/S021812662150287X

access: closed

type: Journal Article

metadata version: 2022-05-18

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  - https://dblp.org/rec/journals/jcsc/SahuBP21
Satya Ranjan Sahu, Bandan Kumar Bhoi, Manoranjan Pradhan:
Improved Redundant Binary Adder Realization in FPGA. J. Circuits Syst. Comput. 30(16): 2150287:1-2150287:14 (2021)

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