"Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder."

Subodh Kumar Singhal et al. (2020)

> Home

Details and statistics

DOI: 10.1142/S0218126620501868

access: closed

type: Journal Article

metadata version: 2021-10-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jcsc/SinghalMPS20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcsc/SinghalMPS20
Subodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena:
Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder. J. Circuits Syst. Comput. 29(12): 2050186:1-2050186:20 (2020)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.