"Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test ..."

Senling Wang et al. (2015)

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DOI: 10.1166/JOLPE.2015.1410

access: closed

type: Journal Article

metadata version: 2020-05-22

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Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi:
Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip. J. Low Power Electron. 11(4): 528-540 (2015)

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