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"CMOS implementation of a multiple-valued logic signed-digit full adder ..."

Alejandro F. González et al. (2001)

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DOI: 10.1109/4.924855

access: closed

type: Journal Article

metadata version: 2022-04-04

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Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder:
CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices. IEEE J. Solid State Circuits 36(6): 924-932 (2001)

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