"A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture."

Toshihiko Hirose et al. (1990)

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DOI: 10.1109/4.62126

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type: Journal Article

metadata version: 2025-01-23

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Toshihiko Hirose, Hirotada Kuriyama, Shuji Murakami, Kojiro Yuzuriha, Takao Mukai, Kazuhito Tsutsumi, Yasumasa Nishimura, Yoshio Kohno, Kenji Anami:
A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture. IEEE J. Solid State Circuits 25(5): 1068-1074 (1990)

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