"A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree."

Niichi Itoh et al. (2001)

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DOI: 10.1109/4.902765

access: closed

type: Journal Article

metadata version: 2022-04-06

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Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba:
A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. IEEE J. Solid State Circuits 36(2): 249-257 (2001)

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