"PLL design technique by a loop-trajectory analysis taking decision-circuit ..."

Keiji Kishine et al. (2004)

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DOI: 10.1109/JSSC.2004.826319

access: closed

type: Journal Article

metadata version: 2022-04-22

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Keiji Kishine, Kyoko Fujimoto, Satomi Kusanagi, Haruhiko Ichino:
PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits. IEEE J. Solid State Circuits 39(5): 740-750 (2004)

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