"Improved address buffers, TTL input current reduction, and hidden refresh ..."

Hiroshi Miyamoto et al. (1990)

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DOI: 10.1109/4.52180

access: closed

type: Journal Article

metadata version: 2025-01-23

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Hiroshi Miyamoto, Tadato Yamagata, Shigeru Mori, Tetsuya Aono, Ikuo Ogoh, Michihiro Yamada:
Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM. IEEE J. Solid State Circuits 25(2): 525-530 (1990)

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