"A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m ..."

Junji Mori et al. (1991)

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DOI: 10.1109/4.75061

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type: Journal Article

metadata version: 2025-02-26

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Junji Mori, Masato Nagamatsu, Masashi Hirano, Shigeru Tanaka, Makoto Noda, Yoshiaki Toyoshima, Kazuhiro Hashimoto, Hiroyuki Hayashida, Kenji Maeguchi:
A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology. IEEE J. Solid State Circuits 26(4): 600-606 (1991)

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