"A 29-ns 64-Mb DRAM with hierarchical array architecture."

Masayuki Nakamura et al. (1996)

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DOI: 10.1109/4.535414

access: closed

type: Journal Article

metadata version: 2022-07-18

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  - https://dblp.org/rec/journals/jssc/NakamuraTAKMSAK96
Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato:
A 29-ns 64-Mb DRAM with hierarchical array architecture. IEEE J. Solid State Circuits 31(9): 1302-1307 (1996)

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