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"A reconfigurable multilevel parallel texture cache memory with 75-GB/s ..."

Se-Jeong Park et al. (2002)

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DOI: 10.1109/4.997855

access: closed

type: Journal Article

metadata version: 2022-04-04

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Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kang-Min Lee, Tae-Hum Yang, Jin-Yong Jung, Hoi-Jun Yoo:
A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth. IEEE J. Solid State Circuits 37(5): 612-623 (2002)

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