"A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention ..."

Katsuyuki Sato et al. (1991)

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DOI: 10.1109/4.98972

access: closed

type: Journal Article

metadata version: 2025-02-26

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Katsuyuki Sato, Kanehide Kenmizaki, Shoji Kubono, Toshio Mochizuki, Hidetomo Aoyagi, Michitaro Kanamitsu, Soichi Kunito, Hiroyuki Uchida, Yoshihiko Yasu, Atsushi Ogishima, Sho Sano, Hiroshi Kawamoto:
A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current. IEEE J. Solid State Circuits 26(11): 1556-1562 (1991)

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