Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC."

Chien-Jian Tseng et al. (2012)

> Home

Details and statistics

DOI: 10.1109/JSSC.2012.2192655

access: closed

type: Journal Article

metadata version: 2020-08-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/TsengCSCC12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/TsengCSCC12
Chien-Jian Tseng, Hung-Wei Chen, Wei-Ting Shen, Wei-Chih Cheng, Hsin-Shu Chen:
A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC. IEEE J. Solid State Circuits 47(6): 1334-1343 (2012)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.