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"A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in ..."

Jinn-Shyan Wang et al. (2010)

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DOI: 10.1109/JSSC.2010.2047994

access: closed

type: Journal Article

metadata version: 2020-08-30

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  - https://dblp.org/rec/journals/jssc/WangCLLW10
Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang:
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop. IEEE J. Solid State Circuits 45(5): 1036-1047 (2010)

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