"An FPGA-based binary neural network accelerator with enhanced hardware ..."

Dezheng Zhang et al. (2025)

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DOI: 10.1016/J.MEJO.2025.106556

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type: Journal Article

metadata version: 2025-03-03

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Dezheng Zhang, Rui Cen, Han Pu, Rui Wan, Dong Wang:
An FPGA-based binary neural network accelerator with enhanced hardware efficiency and data reuse. Microelectron. J. 156: 106556 (2025)

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