"A fringing-capacitance model for deep-submicron MOSFET with high-k gate ..."

F. Ji et al. (2008)

> Home

Details and statistics

DOI: 10.1016/J.MICROREL.2008.01.007

access: closed

type: Journal Article

metadata version: 2023-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/mr/JiXLG08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/mr/JiXLG08
F. Ji, Jing-Ping Xu, Pui-To Lai, J. G. Guan:
A fringing-capacitance model for deep-submicron MOSFET with high-k gate dielectric. Microelectron. Reliab. 48(5): 693-697 (2008)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.