"Low-Voltage Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias ..."

Atsuki Kobayashi, Kiichi Niitsu (2020)

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DOI: 10.1109/OJCAS.2020.3007393

access: open

type: Journal Article

metadata version: 2021-07-29

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  - https://dblp.org/rec/journals/ojcands/KobayashiN20
Atsuki Kobayashi, Kiichi Niitsu:
Low-Voltage Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias Switching Technique in 55-nm DDC CMOS. IEEE Open J. Circuits Syst. 1: 107-114 (2020)

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