"Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing ..."

Anuja Sehgal, Krishnendu Chakrabarty (2007)

> Home

Details and statistics

DOI: 10.1109/TC.2007.15

access: closed

type: Journal Article

metadata version: 2007-01-04

- view
  - electronic edition @ ieeecomputersociety.org
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tc/SehgalC07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tc/SehgalC07
Anuja Sehgal, Krishnendu Chakrabarty:
Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs. IEEE Trans. Computers 56(1): 120-133 (2007)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.