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"Computing the entire active area/power consumption versus delay tradeoff ..."

Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess (1996)

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DOI: 10.1109/43.543774

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - journals/tcad/BerkelaarBJ96
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  - https://dblp.org/rec/journals/tcad/BerkelaarBJ96
Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess:
Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11): 1424-1434 (1996)

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