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"Formal verification of memory circuits by switch-level simulation."

Randal E. Bryant (1991)

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DOI: 10.1109/43.62795

access: closed

type: Journal Article

metadata version: 2020-09-24

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Randal E. Bryant:
Formal verification of memory circuits by switch-level simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(1): 94-102 (1991)

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