"An Effective and Efficient Framework for Clock Latency Range Aware Clock ..."

Sheng Chou et al. (2011)

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DOI: 10.1109/TCAD.2011.2110591

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type: Journal Article

metadata version: 2020-09-24

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Sheng Chou, Cheng-Shen Han, Po-Kai Huang, Ko-Fan Tien, Tsung-Yi Ho:
An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(7): 1045-1057 (2011)

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