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"Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for ..."

Hochang Jang, Deokjin Joo, Taewhan Kim (2011)

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DOI: 10.1109/TCAD.2010.2066650

access: closed

type: Journal Article

metadata version: 2020-09-24

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Hochang Jang, Deokjin Joo, Taewhan Kim:
Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 96-109 (2011)

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