"System-level performance analysis for designing on-chipcommunication ..."

Kanishka Lahiri, Anand Raghunathan, Sujit Dey (2001)

> Home

Details and statistics

DOI: 10.1109/43.924830

access: closed

type: Journal Article

metadata version: 2021-10-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/LahiriRD01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/LahiriRD01
Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
System-level performance analysis for designing on-chipcommunication architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 768-783 (2001)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.