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"CMOS circuit verification with symbolic switch-level timingsimulation."
Clayton B. McDonald, Randal E. Bryant (2001)
- Clayton B. McDonald, Randal E. Bryant:
CMOS circuit verification with symbolic switch-level timingsimulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3): 458-474 (2001)
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