"Logic Partitioning for Minimizing Gate Arrays."

Chet A. Palesko, Lex A. Akers (1983)

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DOI: 10.1109/TCAD.1983.1270028

access: closed

type: Journal Article

metadata version: 2020-09-24

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Chet A. Palesko, Lex A. Akers:
Logic Partitioning for Minimizing Gate Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(2): 117-121 (1983)

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