"Register transfer level power optimization with emphasis on glitch ..."

Anand Raghunathan, Sujit Dey, Niraj K. Jha (1999)

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DOI: 10.1109/43.775632

access: closed

type: Journal Article

metadata version: 2021-10-14

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Anand Raghunathan, Sujit Dey, Niraj K. Jha:
Register transfer level power optimization with emphasis on glitch analysis and reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8): 1114-1131 (1999)

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