"Power-Efficient Pipelined Multiprocessor Architecture With Parallel ..."

Ardhendu Sarkar, Surajeet Ghosh (2024)

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DOI: 10.1109/TCAD.2024.3368278

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type: Journal Article

metadata version: 2024-08-22

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Ardhendu Sarkar, Surajeet Ghosh:
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(8): 2365-2378 (2024)

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