"A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory ..."

Yi-Min Lin et al. (2011)

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DOI: 10.1109/TCSII.2011.2161704

access: closed

type: Journal Article

metadata version: 2020-05-27

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Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee:
A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 682-686 (2011)

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