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"A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS."

Kuan-Yueh James Shen et al. (2018)

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DOI: 10.1109/TCSI.2017.2784319

access: closed

type: Journal Article

metadata version: 2021-05-19

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  - https://dblp.org/rec/journals/tcas/ShenFFNWNKE18
Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Mark Neidengard, Nasser A. Kurd, Amr Elshazly:
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2109-2117 (2018)

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