"A 5-Bit 500-MS/s Asynchronous Digital Slope ADC With Two Comparators."

Yujun Shu et al. (2018)

> Home

Details and statistics

DOI: 10.1109/TCSII.2017.2695720

access: closed

type: Journal Article

metadata version: 2020-05-27

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/ShuMYW18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/ShuMYW18
Yujun Shu, Fengyi Mei, Youling Yu, Jiangfeng Wu:
A 5-Bit 500-MS/s Asynchronous Digital Slope ADC With Two Comparators. IEEE Trans. Circuits Syst. II Express Briefs 65-II(4): 426-430 (2018)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.