![](https://dblp.dagstuhl.de/img/logo.ua.320x120.png)
![](https://dblp.dagstuhl.de/img/dropdown.dark.16x16.png)
![](https://dblp.dagstuhl.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.dagstuhl.de/img/search.dark.16x16.png)
![search dblp](https://dblp.dagstuhl.de/img/search.dark.16x16.png)
default search action
"A 90-nm 640 MHz 2 × VDD Output Buffer With 41.5% Slew Rate ..."
Jian-An Wang, Yuan-Yao Zhao, Zhengping Zhang (2020)
- Jian-An Wang, Yuan-Yao Zhao
, Zhengping Zhang:
A 90-nm 640 MHz 2 × VDD Output Buffer With 41.5% Slew Rate Improvement Using PVT Compensation. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1524-1528 (2020)
![](https://dblp.dagstuhl.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.