"Code construction and FPGA implementation of a low-error-floor multi-rate ..."

Lei Yang, Hui Liu, Chuanjin Richard Shi (2006)

> Home

Details and statistics

DOI: 10.1109/TCSI.2005.862074

access: closed

type: Journal Article

metadata version: 2024-07-29

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/YangLS06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/YangLS06
Lei Yang, Hui Liu, Chuanjin Richard Shi:
Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(4): 892-904 (2006)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.