"An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s ..."

Richard Barrie et al. (2025)

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DOI: 10.1109/TCSII.2025.3547997

access: open

type: Journal Article

metadata version: 2025-11-02

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Richard Barrie, Ming Yang, Hossein Shakiba, Anthony Chan Carusone:
An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s Wireline Systems. IEEE Trans. Circuits Syst. II Express Briefs 72(8): 978-982 (2025)

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